UTM Scholar : PROF. MADYA DR. SHAIKH NASIR @ NASIR BIN SHAIKH HUSIN

GRANT(PI & MEMBERS)

35

PUBLICATIONS

58

INDEXED PUBLICATION

29

TOTAL STUDENTS

H-INDEXED (SCOPUS)

CITATIONS (SCOPUS)

Grant (PI)

NATIONAL GRANTS

UNIVERSITY FUND

TOTAL

Publications

INDEXED PUBLICATION

NON-INDEXED PUBLICATION

OTHERS PUBLICATION

TOTAL

Supervisions

MASTER

PHD

TOTAL

Legend : SPONSOR TYPE OF GRANT

Grant Name	Year
Spectral-based Convolutional Neural Network Model for Optical Character Recognition KEMENTERIAN SAINS, TEKNOLOGI DAN INOVASI (MOSTI) TECHNOLOGY DEVELOPMENT FUND	2022
Architectural Exploration and Characterization of Dynamically Reconfigurable Network Processing Middlebox for Network Traffic Management MINISTRY OF EDUCATION Fundamental Research Grant Scheme	2019
TRAFFIC-AWARE MEDIUM ACCESS MECHANISM FOR WIRELESS NETWORK-ON-CHIP RUG OF UTM Tier 2	2019
UTM-TDR25.3(T2):INTERFACE ANALOG ELECTRONIC MODULE USING CARBON BASED ECG SENSOR RUG OF UTM UTM Transdiciplinary Research Grant	2018
Hybrid Reconfigurable Transmitting Power and Adaptive Packet Relocator Scheme in Wireless Network-on-Chip RUG OF UTM Potential Academic Staff	2017
Innovative Arduino hardware development and programming for Sekolah Tun Fatimah and SMK Bandar Tenggara students SEAGATE INTERNATIONAL (JOHOR) SDN. BHD. Networking Grant	2017
Innovative Arduino hardware development and programming for SMK Taman Universiti 1 and SMK Sultan Alauddin students SEAGATE INTERNATIONAL (JOHOR) SDN. BHD. Networking Grant	2017
Interactive Arduino hardware development and programming for secondary school students SEAGATE INTERNATIONAL (JOHOR) SDN. BHD. Networking Grant	2016
Innovative Arduino programming and hardware development to encourage school students to STEM SEAGATE INTERNATIONAL (JOHOR) SDN. BHD. Networking Grant	2016
ASIC DESIGN AND FABRICATION OF ACTOR-BASED SIGNAL PROCESSING SYSTEMS MINISTRY OF ENERGY, SCIENCE, TECHNOLOGY, ENVIRONEMNT AND CLIMATE CHANGE (MESTECC) Sciencefund	2015
HETEROGENEOUS MULTIPROCESSOR SYSTEM-ON-CHIP PROTOTYPING WITH RUN TIME DYNAMIC APPLICATION MAPPING RUG OF UTM Matching Grant	2015
FPGA System-on-Chip Implementation of Advanced Face Recognition Technology for Biometric Verification and Identification at Airports MINISTRY OF ENERGY, SCIENCE, TECHNOLOGY, ENVIRONEMNT AND CLIMATE CHANGE (MESTECC) Sciencefund	2015
Quantum Neural Network Models for Pattern Recognition using FPGA Hardware Emulation MINISTRY OF EDUCATION Fundamental Research Grant Scheme	2014
High-bandwidth image processor to detect ship in real-time for maritime security MINISTRY OF ENERGY, SCIENCE, TECHNOLOGY, ENVIRONEMNT AND CLIMATE CHANGE (MESTECC) Sciencefund	2014
A NETFPGA BASED RECONFIGURABLE MIDDLEBOX FOR QUALITY-OF-SERVICE NETWORK TRAFFIC MINISTRY OF ENERGY, SCIENCE, TECHNOLOGY, ENVIRONEMNT AND CLIMATE CHANGE (MESTECC) Sciencefund	2014
Multiprocessor System-On-Chip Based On Low Latency Network-On-Chip For High-Throughput Traffic Classification On NetFPGA MINISTRY OF EDUCATION Fundamental Research Grant Scheme	2013
i-Sejahtera: AN INTEGRATED INTELLIGENT MONITORING AND MANAGEMENT SYSTEM FOR ENVIRONMENT, HEALTH AND SECURITY-subprogram Security RUG OF UTM Flagship	2013
Cognitive Radio Based Multihop Relay Network RUG OF UTM Tier 1	2012
FPGA-BASED EMBEDDED SYSTEM-ON-CHIP DESIGN OF ULTRASOUND POWER MEASUREMENT SYSTEM RUG OF UTM Tier 2	2012
HARDWARE ACCELERATOR FOR AUTOMATIC AERIAL VIDEO OBJECT DETECTION Tier 2	2012
Mobility and Handoff Management for Cognitive Radio Mobile Ad-Hoc Networks (CRMANETs) UNIVERSITI TEKNOLOGI MALAYSIA Tier 2	2012
EMBEDDED MULTIMODAL FINGERVEIN-FINGERPRINT BIOMETRIC SYSTEM IN FPGA HARDWARE RUG OF UTM Tier 1	2011
Dynamic Spectrum Management for Cognitive Radio RUG OF UTM Tier 1	2011
FPGA-based space time mimo-ofdm design for wireless lans MINISTRY OF ENERGY, SCIENCE, TECHNOLOGY, ENVIRONEMNT AND CLIMATE CHANGE (MESTECC) Sciencefund	2006
The Design of Low Power RF Transceiver using Mixed Signal IC Design Technique MINISTRY OF ENERGY, SCIENCE, TECHNOLOGY, ENVIRONEMNT AND CLIMATE CHANGE (MESTECC) Sciencefund	2001
Advanced EDA/CAD Algorithms & Technique for Deep-Submicron IC Design Non Goverment Agency	2001
System-on-chip (SoC) Design of an Intelligent Network Processor Microchip with Data Security Features Sciencefund	1998
Design of a Mixed-Mode, Testable VLSI Neuroprocessor Chip, With Built-in Current Test Sensor Structure, to be Applied in Computer Networking Hardware MINISTRY OF ENERGY, SCIENCE, TECHNOLOGY, ENVIRONEMNT AND CLIMATE CHANGE (MESTECC) Sciencefund	1996
Sub Micron Technology and System-on-Chip (SoC) Design MINISTRY OF ENERGY, SCIENCE, TECHNOLOGY, ENVIRONEMNT AND CLIMATE CHANGE (MESTECC) Sciencefund	1995
Real Time Implementation of Image and Video Coder Using Field Programmable Gate Array (FPGA) Technology for High Speed Multimedia Systems MINISTRY OF ENERGY, SCIENCE, TECHNOLOGY, ENVIRONEMNT AND CLIMATE CHANGE (MESTECC) Sciencefund	1995
Design Of ATM Multicast Switch Architecture For MAGNET MINISTRY OF ENERGY, SCIENCE, TECHNOLOGY, ENVIRONEMNT AND CLIMATE CHANGE (MESTECC) Sciencefund	1995
Rechargeable Alkaline Manganese Battery RD on Cycle And Performance Improvement Contract	1995
Integrated circuit design MINISTRY OF ENERGY, SCIENCE, TECHNOLOGY, ENVIRONEMNT AND CLIMATE CHANGE (MESTECC) Sciencefund	1987

Legend : PUBLICATION CATEGORY TYPE OF AUTHORS

Publication Name	Year
INTERFACE ANALOG ELECTRONIC MODULE USING CARBON BASED ECG SENSOR Clasified/Technical Report CO-AUTHOR	2023
Accurate And Compact Convolutional Neural Network Based On Stochastic Computing NEUROCOMPUTING Publication In Web Of Science CO-AUTHOR	2022
Smart Attendance And Notify Me Apps PROC. OF EE CAPSTONE SHOWCASE (EECS2020) Proceedings CORRESPONDING AUTHOR	2021
Dplbant: Improved Load Balancing Technique Based On Detection And Rerouting Of Elephant Flows In Software-Defined Networks COMPUTER COMMUNICATIONS Publication In Web Of Science CO-AUTHOR	2021
Low-Area And Accurate Inner Product And Digital Filters Based On Stochastic Computing SIGNAL PROCESSING Publication In Web Of Science CO-AUTHOR	2021
Cntfet Based Voltage Mode Miso Active Only Biquadratic Filter For Multi‑Ghz Frequency Applications CIRCUITS SYSTEMS AND SIGNAL PROCESSING Publication In Web Of Science CO-AUTHOR	2021
Stochastic Computing Low-Pass Iir Filter Asic Design Using Or Gate Adder PROCEEDINGS OF 2021 ELECTRICAL ENGINEERING SYMPOSIUM (EES2021) Proceedings UTM FIRST AUTHOR	2021
Stochastic Computing Robert Cross’S Detector Asic Design PROCEEDINGS OF 2021 ELECTRICAL ENGINEERING SYMPOSIUM (EES2021) Proceedings UTM FIRST AUTHOR	2021
Stochastic Computing Low-Pass Fir Filter Asic Design Using Or Adder PROCEEDINGS OF 2021 ELECTRICAL ENGINEERING SYMPOSIUM (EES2021) Proceedings CORRESPONDING AUTHOR	2021
Incorporating Industry Grade Mentor Graphics Tcad Tool In Vlsi Project Assignment NEW ACADEMIA LEARNING INNOVATION 2021 Proceedings CO-AUTHOR	2021
Vlsi Design Of Hardware Efficient Present Encryption PROCEEDINGS OF 2020 ELECTRICAL ENGINEERING SYMPOSIUM (EES2020) Proceedings CORRESPONDING AUTHOR	2020
Characterization Of Correlation In Stochastic Computing Functions 2ND INTERNATIONAL CONFERENCE ON ELECTRICAL, COMMUNICATION AND COMPUTER ENGINEERING Publication In Scopus CO-AUTHOR	2020
DESIGN AND CHARACTERIZATION ON SCHEMATIC AND LAYOUT OF COMPLEX BOOLEAN EXPRESSION USING MENTOR GRAPHICS Modules / Manual CO-AUTHOR	2020
Asic Design Of A Shortest-Path Processor Core PROCEEDINGS OF 2020 ELECTRICAL ENGINEERING SYMPOSIUM (EES2020) Proceedings UTM FIRST AUTHOR	2020
Vlsi Design Of Harris Corner Detector PROCEEDINGS OF 2020 ELECTRICAL ENGINEERING SYMPOSIUM (EES2020) Proceedings UTM FIRST AUTHOR	2020
Interleaved Incremental/Decremental Support Vector Machine For Embedded System IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (IEEE ISCAS) Publication In Web Of Science UTM FIRST AUTHOR	2019
Vlsi Implementation Of Present Encryption Algorithm PROCEEDINGS OF 2019 ELECTRICAL ENGINEERING SYMPOSIUM (EES2019) Proceedings CORRESPONDING AUTHOR	2019
A Cntfet-C First Order All Pass Filter ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING Publication In Web Of Science CO-AUTHOR	2019
Design Of Voltage Mode Electronically Tunable First Order All Pass Filter In +/- 0.7 V 16 Nm Cnfet Technology ELECTRONICS Publication In Web Of Science CO-AUTHOR	2019
A Streaming Multi-Class Support Vector Machine Classification Architecture For Embedded Systems INDONESIAN JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE Publication In Scopus UTM FIRST AUTHOR	2019
Accurate And Compact Stochastic Computations By Exploiting Correlation TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES Publication In Web Of Science CO-AUTHOR	2019
Vlsi Design Of Bluetooth Link Layer Controller PROCEEDINGS OF 2019 ELECTRICAL ENGINEERING SYMPOSIUM (EES2019) Proceedings CORRESPONDING AUTHOR	2019
Performance Evaluation Of Centralized Reconfigurable Transmitting Power Scheme In Wireless Network-On-Chip TELKOMNIKA Publication In Scopus CO-AUTHOR	2018
Bluetooth Low Energy Link Layer Controller PROCEEDINGS OF 2018 ELECTRICAL ENGINEERING SYMPOSIUM (EES2018) VOL. 3 Proceedings UTM FIRST AUTHOR	2018
Stochastic Computing Correlation Utilization In Convolutional Neural Network Basic Functions TELKOMNIKA (TELECOMMUNICATION, COMPUTING, ELECTRONICS AND CONTROL) Publication In Scopus CO-AUTHOR	2018
Algorithm To Convert Signal Interpreted Petri Net Models To Programmable Logic Controller Ladder Logic Diagram Models INDONESIAN JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE Publication In Scopus CO-AUTHOR	2018
A Linked List Run-Length-Based Single-Pass Connected Component Analysis For Real-Time Embedded Hardware JOURNAL OF REAL-TIME IMAGE PROCESSING Publication In Web Of Science CO-AUTHOR	2018
Hardware Transactional Memory Architecture With Adaptive Version Management For Multi-Processor Fpga Platforms JOURNAL OF SYSTEMS ARCHITECTURE Publication In Web Of Science CO-AUTHOR	2017
ELECTRONIC WORKSHOP FOR SCHOOL STUDENTS Modules / Manual CO-AUTHOR	2017
Runtime Network-On-Chip Thermal And Power Balancing APPLICATIONS OF MODELING AND SIMULATION Journal Article Non Citation-Indexed CO-AUTHOR	2017
Reconfigurable Logic Embedded Architecture Of Support Vector Machine Linear Kernel 2017 4TH INTERNATIONAL CONFERENCE ON ELECTRICAL ENGINEERING, COMPUTER SCIENCE AND INFORMATICS (EECSI 2017) Conference Paper CO-AUTHOR	2017
An Optimized Buffer Insertion Algorithm With Delay-Power Constraints For Vlsi Layouts TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES Publication In Scopus UTM FIRST AUTHOR	2017
Implementation Of Parallel Harris Corner Detector On Fpga PROCEEDINGS OF 2017 ELECTRICAL ENGINEERING SYMPOSIUM (EES2017) Proceedings UTM FIRST AUTHOR	2017
Application Profiling And Mapping On Noc-Based Mpsoc Emulation Platform On Reconfigurable Logic TELKOMNIKA (TELECOMMUNICATION COMPUTING ELECTRONICS AND CONTROL) Publication In Scopus UTM FIRST AUTHOR	2017
LAB SHEETS CAPSTONE PROJECT DESIGN Clasified/Technical Report CO-AUTHOR	2016
Hardware Acceleration Of A Face Detection System On Fpga IEEE STUDENT CONF. ON RESEARCH AND DEVELOPMENT SCORED 2015 Publication In Scopus CO-AUTHOR	2016
Dynamic Power Dissipation Formulation For Application In Dynamic Programming Buffer Insertion Algorithm JURNAL TEKNOLOGI (SCIENCES & ENGINEERING) Publication In Scopus UTM FIRST AUTHOR	2016
HIGHBANDWIDTH IMAGE PROCESSOR TO DETECT SHIP IN REALTIME FOR MARITIME SECURITY Clasified/Technical Report CORRESPONDING AUTHOR	2016
Fpga-Based Real-Time Moving Target Detection System For Unmanned Aerial Vehicle Application INTERNATIONAL JOURNAL OF RECONFIGURABLE COMPUTING Publication In Web Of Science CORRESPONDING AUTHOR	2016
Low Cost Pipelined Fpga Architecture Of Harris Corner Detector For Real-Time Applications THE 10TH INTERNATIONAL CONFERENCE ON DIGITAL INFORMATION MANAGEMENT, ICDIM 2015 Publication In Scopus UTM FIRST AUTHOR	2016
An Optimized Algorithm For Simultaneous Routing And Buffer Insertion In Multi-Terminal Nets ARPN JOURNAL OF ENGINEERING AND APPLIED SCIENCES Journal Article Non Citation-Indexed UTM FIRST AUTHOR	2015
Sleep Apnea Event Detection System Based On Heart Rate Variability Analysis THE SECOND INTERNATIONAL CONFERENCE ON ADVANCED DATA AND INFORMATION ENGINEERING Conference Paper CO-AUTHOR	2015
Survey On Multi Field Packet Classification Techniques RESEARCH JOURNAL OF RECENT SCIENCES Journal Article Non Citation-Indexed UTM FIRST AUTHOR	2015
Adaptive Configurable Transactional Memory For Multi-Processor Fpga Platforms 2015 IEEE 23RD ANNUAL INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, FCCM 2015 Publication In Scopus CO-AUTHOR	2015
An Optimization Algorithm For Simultaneous Routing And Buffer Insertion With Delay-Power Constraints In Vlsi Layout Design 15TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, ISQED 2014 Publication In Scopus UTM FIRST AUTHOR	2014
Hardware Transactional Memory On Multi-Processor Fpga Platform THE IEEE INTERNATIONAL SYMPOSIUM ON CIRCUIT AND SYSTEMS 2014 (ISCASÃƒÂ¢Ã‚Â€Ã‚Â™2014) Publication In Scopus CO-AUTHOR	2014
Remote Dynamically Reconfigurable Platform Using Netfpga PROCEEDINGS - IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS Publication In Scopus CO-AUTHOR	2014
An Empirical Evaluation Of Topologies For Large Scale Noc TELKOMNIKA INDONESIAN JOURNAL OF ELECTRICAL ENGINEERING Journal Article Non Citation-Indexed UTM FIRST AUTHOR	2014
Network Partitioning Domain Knowledge Multiobjective Application Mapping For Large-Scale Network-On-Chip APPLIED COMPUTATIONAL INTELLIGENCE AND SOFT COMPUTING Journal Article Non Citation-Indexed CO-AUTHOR	2014
Energy-Aware Network-On-Chip Application Mapping Based On Domain Knowledge Genetic Algorithm THE 2014 IAES INTERNATIONAL CONFERENCE ON ELECTRICAL ENGINEERING, COMPUTER SCIENCE AND INFORMATICS (EECSI 2014) Proceedings CO-AUTHOR	2014
Configurable Version Management Hardware Transactional Memory For Multi-Processor Platform THE 2014 IAES INTERNATIONAL CONFERENCE ON ELECTRICAL ENGINEERING, COMPUTER SCIENCE AND INFORMATICS (EECSI 2014) Proceedings CO-AUTHOR	2014
Feasible Transition Path Generation For Efsm-Based System Testing IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS Publication In Web Of Science CO-AUTHOR	2013
Network Partitioning And Ga Heuristic Crossover For Noc Application Mapping IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS Publication In Web Of Science CO-AUTHOR	2013
S.Rabila2: An Optimal Vlsi Routing Algorithm With Buffer Insertion Using Iterative Rlc Model ICCAS 2012 - 2012 IEEE INTERNATIONAL CONFERENCE ON CIRCUITS AND SYSTEMS: "ADVANCED CIRCUITS AND SYSTEMS FOR SUSTAINABILITY" Publication In Scopus CO-AUTHOR	2012
Iterative Rlc Models For Interconnect Delay Optimization In Vlsi Routing Algorithms Advances in Microelectronics Book Chapter CO-AUTHOR	2009
Simultaneous Routing And Buffer Insertion Algorithm For Minimizing Interconnect Delay In Vlsi Layout Design Advances in Microelectronics Book Chapter UTM FIRST AUTHOR	2009
- Advances In Microelectronics Original Book UTM FIRST AUTHOR	2009
Malaysian Journal Of Computer Science An Optimization Algorithm Based On Grid-Graphs for Minimizing Interconnect Delay In VLSI Layout Design Publication In Scopus CO-AUTHOR	2009

Legend : IP CATEGORY IP LEVEL

Intellectual Property Name	Grant Register No.	IP Level	IP Category
HRTB-LA SOFTWARE FOR ROUTING VLSI INTERCONNECT	LY2017001974	NATIONAL	COPYRIGHT
DESIGN AND CHARACTERIZATION ON SCHEMATIC AND LAYOUT OF COMPLEX BOOLEAN EXPRESSION USING MENTOR GRAPHICS EDA TOOL	IP/CR/01281	NATIONAL	COPYRIGHT

Legend : SESSION LEVEL OF STUDY STATUS SUPERVISION LEVEL

Supervision List
CHESSDA UTTRAPHAN A/L EH KAN INTERCONNECT TREE OPTIMIZATION ALGORITHM IN NANOMETRE VERY LARGE SCALE INTEGRATION DESIGNS PHD GRADUATED SUPERVISOR 2015
AHMED ABDALLA MOHAMEDALI ABDALLA DATASET GENERATION AND NETWORK INTRUSION DETECTION BASED ON FLOW-LEVEL INFORMATION PHD GRADUATED SUPERVISOR 2015
MEHDI BABOLI CLUSTERED TWO - DIMENSIONAL MESH TOPOLOGY FOR LARGE - SCALE NETWORK - ON - CHIP ARCHITECTURE PHD GRADUATED SUPERVISOR 2017
HAMDAN USAMAH HAMDAN ABDELLATEF STOCHASTIC COMPUTING SYSTEM HARDWARE DESIGN FOR CONVOLUTIONAL NEURAL NETWORKS OPTIMIZED FOR ACCURACY, AREA AND ENERGY EFFICIENCY PHD GRADUATED CO-SUPERVISOR 2019
JEEVAN A/L SIRKUNAN INTERLEAVED INCREMENTAL-DECREMENTAL SUPPORT VECTOR MACHINE FOR EMBEDDED APPLICATIONS PHD GRADUATED CO-SUPERVISOR 2022
TANG JIA WEI ACCELERATED EMULATION-BASED APPLICATION MAPPING BASED ON NETWORK-ON-CHIP COMMUNICATION DELAY MODEL MASTER GRADUATED SUPERVISOR 2013
MUHD FIRDAUS BIN MUHD YUSOFF MASTER GRADUATED SUPERVISOR 2014
AWAIS GUL AIRIJ GUL MULTIMODAL ADAPTIVE ALGORITHM FOR STRESS CLASSIFICATION IN CHILDREN WITH AUTISM SPECTRUM DISORDER USING CASE-BASED REASONING METHODOLOGY &NBSP; MASTER GRADUATED SUPERVISOR 2015
MOHAMMED OMAR AWADH AL-SHATARI MASTER GRADUATED SUPERVISOR 2016
MUHAMMAD AMIN BIN HASHIM REAL-TIME ARRHYTHMIA CLASSFIER HARDWARE/SOFTWARE ARCHITECTURE ON FIELD PROGRAMMABLE GATE ARRAY MASTER GRADUATED SUPERVISOR 2016
VIDYA DHARAN A/L SRI DARAN NAMBIAR A FACE RECOGNITION SYSTEM ACCELERATED ON EMBEDDED GRAPHICS PROCESSING UNIT ENABLED BY COMPUTE UNIFIED DEVICE ARCHITECTURE MASTER GRADUATED CO-SUPERVISOR 2017