SHAIKH NASIR @ NASIR BIN SHAIKH HUSIN

PROFESOR MADYA (DS54)

Grant (PI and Member)

32

Publication

46

Indexed Publication

23

H-Index (SCOPUS)

Citations (SCOPUS)

Note: List of all research grants and publications shown are based on data registered in RADIS

About Me

nasirsh@utm.my

FACULTY OF ENGINEERING

INNOVATIVE ENGINEERING

-

VLSI DESIGN; DIGITAL SYSTEM DESIGN; COMBINATORIAL OPTIMIZATION

Legend : SPONSOR TYPE OF GRANT

# Grant Name Year
1 Architectural Exploration and Characterization of Dynamically Reconfigurable Network Processing Middlebox for Network Traffic Management
MINISTRY OF EDUCATION Fundamental Research Grant Scheme
2019
2 TRAFFIC-AWARE MEDIUM ACCESS MECHANISM FOR WIRELESS NETWORK-ON-CHIP
RUG OF UTM Tier 2
2019
3 UTM-TDR25.3(T2):INTERFACE ANALOG ELECTRONIC MODULE USING CARBON BASED ECG SENSOR
RUG OF UTM UTM Transdiciplinary Research Grant
2018
4 Hybrid Reconfigurable Transmitting Power and Adaptive Packet Relocator Scheme in Wireless Network-on-Chip
RUG OF UTM Potential Academic Staff
2017
5 Innovative Arduino hardware development and programming for Sekolah Tun Fatimah and SMK Bandar Tenggara students
SEAGATE INTERNATIONAL (JOHOR) SDN. BHD. Networking Grant
2017
6 Innovative Arduino hardware development and programming for SMK Taman Universiti 1 and SMK Sultan Alauddin students
SEAGATE INTERNATIONAL (JOHOR) SDN. BHD. Networking Grant
2017
7 Interactive Arduino hardware development and programming for secondary school students
SEAGATE INTERNATIONAL (JOHOR) SDN. BHD. Networking Grant
2016
8 Innovative Arduino programming and hardware development to encourage school students to STEM
SEAGATE INTERNATIONAL (JOHOR) SDN. BHD. Networking Grant
2016
9 ASIC DESIGN AND FABRICATION OF ACTOR-BASED SIGNAL PROCESSING SYSTEMS
Sciencefund
2015
10 HETEROGENEOUS MULTIPROCESSOR SYSTEM-ON-CHIP PROTOTYPING WITH RUN TIME DYNAMIC APPLICATION MAPPING
RUG OF UTM Matching Grant
2015
11 FPGA System-on-Chip Implementation of Advanced Face Recognition Technology for Biometric Verification and Identification at Airports
Sciencefund
2015
12 Quantum Neural Network Models for Pattern Recognition using FPGA Hardware Emulation
MINISTRY OF EDUCATION Fundamental Research Grant Scheme
2014
13 High-bandwidth image processor to detect ship in real-time for maritime security
Sciencefund
2014
14 A NETFPGA BASED RECONFIGURABLE MIDDLEBOX FOR QUALITY-OF-SERVICE NETWORK TRAFFIC
Sciencefund
2014
15 Multiprocessor System-On-Chip Based On Low Latency Network-On-Chip For High-Throughput Traffic Classification On NetFPGA
MINISTRY OF EDUCATION Fundamental Research Grant Scheme
2013
16 i-Sejahtera: AN INTEGRATED INTELLIGENT MONITORING AND MANAGEMENT SYSTEM FOR ENVIRONMENT, HEALTH AND SECURITY-subprogram Security
RUG OF UTM Flagship
2013
17 Cognitive Radio Based Multihop Relay Network
RUG OF UTM Tier 1
2012
18 FPGA-BASED EMBEDDED SYSTEM-ON-CHIP DESIGN OF ULTRASOUND POWER MEASUREMENT SYSTEM
RUG OF UTM Tier 2
2012
19 HARDWARE ACCELERATOR FOR AUTOMATIC AERIAL VIDEO OBJECT DETECTION
Tier 2
2012
20 Mobility and Handoff Management for Cognitive Radio Mobile Ad-Hoc Networks (CRMANETs)
UNIVERSITI TEKNOLOGI MALAYSIA Tier 2
2012
21 EMBEDDED MULTIMODAL FINGERVEIN-FINGERPRINT BIOMETRIC SYSTEM IN FPGA HARDWARE
RUG OF UTM Tier 1
2011
22 Dynamic Spectrum Management for Cognitive Radio
RUG OF UTM Tier 1
2011
23 FPGA-based space time mimo-ofdm design for wireless lans
Sciencefund
2006
24 The Design of Low Power RF Transceiver using Mixed Signal IC Design Technique
Sciencefund
2001
25 Advanced EDA/CAD Algorithms & Technique for Deep-Submicron IC Design
Others
2001
26 System-on-chip (SoC) Design of an Intelligent Network Processor Microchip with Data Security Features
Sciencefund
1998
27 Design of a Mixed-Mode, Testable VLSI Neuroprocessor Chip, With Built-in Current Test Sensor Structure, to be Applied in Computer Networking Hardware
Sciencefund
1996
28 Sub Micron Technology and System-on-Chip (SoC) Design
Sciencefund
1995
29 Real Time Implementation of Image and Video Coder Using Field Programmable Gate Array (FPGA) Technology for High Speed Multimedia Systems
Sciencefund
1995
30 Design Of ATM Multicast Switch Architecture For MAGNET
Sciencefund
1995
31 Rechargeable Alkaline Manganese Battery RD on Cycle And Performance Improvement
Contract
1995
32 Integrated circuit design
Sciencefund
1987

Legend : PUBLICATION CATEGORY TYPE OF AUTHORS

# Publication Name Year
1
DESIGN AND CHARACTERIZATION ON SCHEMATIC AND LAYOUT OF COMPLEX BOOLEAN EXPRESSION USING MENTOR GRAPHICS
Modules / Manual CO-AUTHOR
2020
2 Vlsi Design Of Hardware Efficient Present Encryption
PROCEEDINGS OF 2020 ELECTRICAL ENGINEERING SYMPOSIUM (EES2020)
Proceedings CORRESPONDING AUTHOR
2020
3 Asic Design Of A Shortest-Path Processor Core
PROCEEDINGS OF 2020 ELECTRICAL ENGINEERING SYMPOSIUM (EES2020)
Proceedings UTM FIRST AUTHOR
2020
4 Vlsi Design Of Harris Corner Detector
PROCEEDINGS OF 2020 ELECTRICAL ENGINEERING SYMPOSIUM (EES2020)
Proceedings UTM FIRST AUTHOR
2020
5 Characterization Of Correlation In Stochastic Computing Functions
2ND INTERNATIONAL CONFERENCE ON ELECTRICAL, COMMUNICATION AND COMPUTER ENGINEERING
Publication In Scopus CO-AUTHOR
2020
6 Vlsi Implementation Of Present Encryption Algorithm
PROCEEDINGS OF 2019 ELECTRICAL ENGINEERING SYMPOSIUM (EES2019)
Proceedings CORRESPONDING AUTHOR
2019
7 Vlsi Design Of Bluetooth Link Layer Controller
PROCEEDINGS OF 2019 ELECTRICAL ENGINEERING SYMPOSIUM (EES2019)
Proceedings CORRESPONDING AUTHOR
2019
8 Design Of Voltage Mode Electronically Tunable First Order All Pass Filter In +/- 0.7 V 16 Nm Cnfet Technology
ELECTRONICS
Publication In Web Of Science CO-AUTHOR
2019
9 A Streaming Multi-Class Support Vector Machine Classification Architecture For Embedded Systems
INDONESIAN JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE
Publication In Scopus UTM FIRST AUTHOR
2019
10 Interleaved Incremental/Decremental Support Vector Machine For Embedded System
IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (IEEE ISCAS)
Publication In Web Of Science UTM FIRST AUTHOR
2019
11 A Cntfet-C First Order All Pass Filter
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
Publication In Web Of Science CO-AUTHOR
2019
12 Accurate And Compact Stochastic Computations By Exploiting Correlation
TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES
Publication In Web Of Science CO-AUTHOR
2019
13 Bluetooth Low Energy Link Layer Controller
PROCEEDINGS OF 2018 ELECTRICAL ENGINEERING SYMPOSIUM (EES2018) VOL. 3
Proceedings UTM FIRST AUTHOR
2018
14 Algorithm To Convert Signal Interpreted Petri Net Models To Programmable Logic Controller Ladder Logic Diagram Models
INDONESIAN JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE
Publication In Scopus CO-AUTHOR
2018
15 Performance Evaluation Of Centralized Reconfigurable Transmitting Power Scheme In Wireless Network-On-Chip
TELKOMNIKA
Publication In Scopus CO-AUTHOR
2018
16 Stochastic Computing Correlation Utilization In Convolutional Neural Network Basic Functions
TELKOMNIKA (TELECOMMUNICATION, COMPUTING, ELECTRONICS AND CONTROL)
Publication In Scopus CO-AUTHOR
2018
17 A Linked List Run-Length-Based Single-Pass Connected Component Analysis For Real-Time Embedded Hardware
JOURNAL OF REAL-TIME IMAGE PROCESSING
Publication In Web Of Science CO-AUTHOR
2018
18 Reconfigurable Logic Embedded Architecture Of Support Vector Machine Linear Kernel
2017 4TH INTERNATIONAL CONFERENCE ON ELECTRICAL ENGINEERING, COMPUTER SCIENCE AND INFORMATICS (EECSI 2017)
Conference Paper CO-AUTHOR
2017
19 An Optimized Buffer Insertion Algorithm With Delay-Power Constraints For Vlsi Layouts
TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES
Publication In Scopus UTM FIRST AUTHOR
2017
20 Runtime Network-On-Chip Thermal And Power Balancing
APPLICATIONS OF MODELING AND SIMULATION
Journal Article Non Citation-Indexed CO-AUTHOR
2017
21 Hardware Transactional Memory Architecture With Adaptive Version Management For Multi-Processor Fpga Platforms
JOURNAL OF SYSTEMS ARCHITECTURE
Publication In Web Of Science CO-AUTHOR
2017
22 Implementation Of Parallel Harris Corner Detector On Fpga
PROCEEDINGS OF 2017 ELECTRICAL ENGINEERING SYMPOSIUM (EES2017)
Proceedings UTM FIRST AUTHOR
2017
23
ELECTRONIC WORKSHOP FOR SCHOOL STUDENTS
Modules / Manual CO-AUTHOR
2017
24 Fpga-Based Real-Time Moving Target Detection System For Unmanned Aerial Vehicle Application
INTERNATIONAL JOURNAL OF RECONFIGURABLE COMPUTING
Publication In Web Of Science CORRESPONDING AUTHOR
2016
25
HIGHBANDWIDTH IMAGE PROCESSOR TO DETECT SHIP IN REALTIME FOR MARITIME SECURITY
Clasified/Technical Report CORRESPONDING AUTHOR
2016
26 Hardware Acceleration Of A Face Detection System On Fpga
IEEE STUDENT CONF. ON RESEARCH AND DEVELOPMENT SCORED 2015
Publication In Scopus CO-AUTHOR
2016
27
LAB SHEETS CAPSTONE PROJECT DESIGN
Clasified/Technical Report CO-AUTHOR
2016
28 Low Cost Pipelined Fpga Architecture Of Harris Corner Detector For Real-Time Applications
THE 10TH INTERNATIONAL CONFERENCE ON DIGITAL INFORMATION MANAGEMENT, ICDIM 2015
Publication In Scopus UTM FIRST AUTHOR
2016
29 Dynamic Power Dissipation Formulation For Application In Dynamic Programming Buffer Insertion Algorithm
JURNAL TEKNOLOGI (SCIENCES & ENGINEERING)
Publication In Scopus UTM FIRST AUTHOR
2016
30 Adaptive Configurable Transactional Memory For Multi-Processor Fpga Platforms
2015 IEEE 23RD ANNUAL INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, FCCM 2015
Publication In Scopus CO-AUTHOR
2015
31 Survey On Multi Field Packet Classification Techniques
RESEARCH JOURNAL OF RECENT SCIENCES
Journal Article Non Citation-Indexed UTM FIRST AUTHOR
2015
32 Sleep Apnea Event Detection System Based On Heart Rate Variability Analysis
THE SECOND INTERNATIONAL CONFERENCE ON ADVANCED DATA AND INFORMATION ENGINEERING
Conference Paper CO-AUTHOR
2015
33 An Optimized Algorithm For Simultaneous Routing And Buffer Insertion In Multi-Terminal Nets
ARPN JOURNAL OF ENGINEERING AND APPLIED SCIENCES
Journal Article Non Citation-Indexed UTM FIRST AUTHOR
2015
34 Hardware Transactional Memory On Multi-Processor Fpga Platform
THE IEEE INTERNATIONAL SYMPOSIUM ON CIRCUIT AND SYSTEMS 2014 (ISCAS’2014)
Publication In Scopus CO-AUTHOR
2014
35 An Optimization Algorithm For Simultaneous Routing And Buffer Insertion With Delay-Power Constraints In Vlsi Layout Design
15TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, ISQED 2014
Publication In Scopus UTM FIRST AUTHOR
2014
36 Remote Dynamically Reconfigurable Platform Using Netfpga
PROCEEDINGS - IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS
Publication In Scopus CO-AUTHOR
2014
37 Network Partitioning Domain Knowledge Multiobjective Application Mapping For Large-Scale Network-On-Chip
APPLIED COMPUTATIONAL INTELLIGENCE AND SOFT COMPUTING
Journal Article Non Citation-Indexed CO-AUTHOR
2014
38 An Empirical Evaluation Of Topologies For Large Scale Noc
TELKOMNIKA INDONESIAN JOURNAL OF ELECTRICAL ENGINEERING
Journal Article Non Citation-Indexed UTM FIRST AUTHOR
2014
39 Energy-Aware Network-On-Chip Application Mapping Based On Domain Knowledge Genetic Algorithm
THE 2014 IAES INTERNATIONAL CONFERENCE ON ELECTRICAL ENGINEERING, COMPUTER SCIENCE AND INFORMATICS (EECSI 2014)
Proceedings CO-AUTHOR
2014
40 Configurable Version Management Hardware Transactional Memory For Multi-Processor Platform
THE 2014 IAES INTERNATIONAL CONFERENCE ON ELECTRICAL ENGINEERING, COMPUTER SCIENCE AND INFORMATICS (EECSI 2014)
Proceedings CO-AUTHOR
2014
41 Network Partitioning And Ga Heuristic Crossover For Noc Application Mapping
IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS
Publication In Web Of Science CO-AUTHOR
2013
42 Feasible Transition Path Generation For Efsm-Based System Testing
IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS
Publication In Web Of Science CO-AUTHOR
2013
43 Iterative Rlc Models For Interconnect Delay Optimization In Vlsi Routing Algorithms
Advances in Microelectronics
Book Chapter CO-AUTHOR
2009
44 Malaysian Journal Of Computer Science
An Optimization Algorithm Based On Grid-Graphs for Minimizing Interconnect Delay In VLSI Layout Design
Publication In Scopus CO-AUTHOR
2009
45 Simultaneous Routing And Buffer Insertion Algorithm For Minimizing Interconnect Delay In Vlsi Layout Design
Advances in Microelectronics
Book Chapter UTM FIRST AUTHOR
2009
46 -
Advances In Microelectronics
Original Book UTM FIRST AUTHOR
2009

Legend : SUPERVISION LEVEL LEVEL OF STUDY STATUS

# Supervision List
1 AHMED ABDALLA MOHAMEDALI ABDALLA
DATASET GENERATION AND NETWORK INTRUSION DETECTION BASED ON FLOW-LEVEL INFORMATION
SUPERVISOR PHD GRADUATED
2 CHESSDA UTTRAPHAN A/L EH KAN
INTERCONNECT TREE OPTIMIZATION ALGORITHM IN NANOMETRE VERY LARGE SCALE INTEGRATION DESIGNS
SUPERVISOR PHD GRADUATED
3 MEHDI BABOLI
CLUSTERED TWO - DIMENSIONAL MESH TOPOLOGY FOR LARGE - SCALE NETWORK - ON - CHIP ARCHITECTURE
SUPERVISOR PHD GRADUATED
4 HAMDAN USAMAH HAMDAN ABDELLATEF
STOCHASTIC COMPUTING SYSTEM HARDWARE DESIGN FOR CONVOLUTIONAL NEURAL NETWORKS OPTIMIZED FOR ACCURACY, AREA AND ENERGY EFFICIENCY
CO-SUPERVISOR PHD GRADUATED
5 MUHAMMAD IDREES MASUD
DESIGN OF CNTFET BASED ANALOG SIGNAL PROCESSING MODULES
CO-SUPERVISOR PHD ON GOING
6 ANAM RAJPER
HARDWARE ACCELERATED DETECTION AND MITIGATION OF DISTRIBUTED DENIAL OF SERVICE ATTACKS IN SOFTWARE-DEFINED NETWORKS 
SUPERVISOR PHD ON GOING
7 MUNIRAH BINTI AB. RAHMAN
CONGESTION-AWARE LOAD-BALANCED PARTIAL ADAPTIVE ROUTING IN WIRELESS NETWORK-ON-CHIP  
CO-SUPERVISOR PHD ON GOING
8 JEEVAN A/L SIRKUNAN
INTERLEAVED INCREMENTAL SUPPORT VECTOR MACHINEFOR EMBEDDED APPLICATIONS
CO-SUPERVISOR PHD ON GOING
9 TANG JIA WEI
ACCELERATED EMULATION-BASED APPLICATION MAPPING BASED ON NETWORK-ON-CHIP COMMUNICATION DELAY MODEL
SUPERVISOR MASTER GRADUATED
10 WAHEEDA JABBAR
RESOURCE ALLOCATION SCHEME FOR FUTURE USER-CENTRIC WIRELESS NETWORK
SUPERVISOR MASTER GRADUATED
11 MUHD FIRDAUS BIN MUHD YUSOFF

SUPERVISOR MASTER GRADUATED
12 AWAIS GUL AIRIJ GUL
MULTIMODAL ADAPTIVE ALGORITHM FOR STRESS CLASSIFICATION IN CHILDREN WITH AUTISM SPECTRUM DISORDER USING CASE-BASED REASONING METHODOLOGY  
SUPERVISOR MASTER GRADUATED
13 MOHAMMED OMAR AWADH AL-SHATARI

SUPERVISOR MASTER GRADUATED
14 MUHAMMAD AMIN BIN HASHIM
REAL-TIME ARRHYTHMIA CLASSFIER HARDWARE/SOFTWARE ARCHITECTURE ON FIELD PROGRAMMABLE GATE ARRAY
SUPERVISOR MASTER GRADUATED
15 VIDYA DHARAN A/L SRI DARAN NAMBIAR
A FACE RECOGNITION SYSTEM ACCELERATED ON EMBEDDED GRAPHICS PROCESSING UNIT ENABLED BY COMPUTE UNIFIED DEVICE ARCHITECTURE
CO-SUPERVISOR MASTER GRADUATED

Grant (PI)

NATIONAL GRANTS
4
UNIVERSITY FUND
1
TOTAL

Publications

INDEXED PUBLICATION
23
NON-INDEXED PUBLICATION
5
OTHERS PUBLICATION
18
TOTAL

Supervision

DEGREE
0
MASTER
7
PHD
8
TOTAL