MOHAMED KHALIL BIN MOHD HANI

PROFESOR (V)

Grant (PI and Member)

29

Publication

47

Indexed Publication

35

H-Index (SCOPUS)

Citations (SCOPUS)

Note: List of all research grants and publications shown are based on data registered in RADIS

About Me

khalil@utm.my

FACULTY OF ENGINEERING

INNOVATIVE ENGINEERING

-

SYSTEM-ON-CHIP DESIGN; NEUROHARDWARE; IMAGE RECOGNITION; ENCRYPTION

Legend : SPONSOR TYPE OF GRANT

# Grant Name Year
1 A Novel and Smart Arrhythmia Analyzer Design based on Enhanced Artificial Intelligence Algorithm for Cardiac Home Monitoring
MINISTRY OF EDUCATION Transdiscplinary Research Grant Scheme
2016
2 MY-TELECARDIOLOGY: A WEB-BASED TELECARDIOLOGY FRAMEWORK FOR CARDIAC DISEASE PREVENTION AND MONITORING IN MALAYSIA COMMUNITY
RUG OF UTM Tier 1
2015
3 FPGA System-on-Chip Implementation of Advanced Face Recognition Technology for Biometric Verification and Identification at Airports
Sciencefund
2015
4 Novel Dataflow Actor Network Partitioning Algorithms for Multiple FPGAs Systems Implementation
MINISTRY OF EDUCATION Fundamental Research Grant Scheme
2014
5 Fast SoC Prototyping Using Low Latency Hybrid Virtual Platform
COLLABORATIVE RESEARCH IN ENGINEERING, SCIENCE & TECHNOLOGY CENTER (CREST) Others
2014
6 Quantum Neural Network Models for Pattern Recognition using FPGA Hardware Emulation
MINISTRY OF EDUCATION Fundamental Research Grant Scheme
2014
7 A NETFPGA BASED RECONFIGURABLE MIDDLEBOX FOR QUALITY-OF-SERVICE NETWORK TRAFFIC
Sciencefund
2014
8 A Design Framework for Multi-Processor System-on-Chip (MPSoC)Architecture Design-Space Exploration in Biomedical Application: Human Heart ECG Monitoring and Processing
Sciencefund
2013
9 A Real - Time, Intelligent In - Vehicle Driver Drowsiness Detection Device Based On An Embedded System - On - Chip (SOC) In FPGA Microchip Technology
Sciencefund
2011
10 FPGA-Based Secure Embedded System For Personel Authentication Using Finger Vein Biometrics
Sciencefund
2011
11 EMBEDDED MULTIMODAL FINGERVEIN-FINGERPRINT BIOMETRIC SYSTEM IN FPGA HARDWARE
RUG OF UTM Tier 1
2011
12 Hardware Security Module (HSM) and Trusted Computing Platform for Next-Generation E-Security
Technofund
2007
13 CAD Algorithm & Architecture in Physical Design System for Nano-scale VLSI integrated Circuits
MINISTRY OF EDUCATION Fundamental Research Grant Scheme
2007
14 Embedded Soc-Based Hardware Integration Of Compression-Encryption-Authentication For Data Security Of Networked Multi-Gigabyte Databases.
Sciencefund
2006
15 Advanced EDA/CAD Algorithms & Technique for Deep-Submicron IC Design
Others
2001
16 Design of RSA Crypto Coprocessor for Smart Card Microchip
Contract
2001
17 System-on-chip (SoC) Design of an Intelligent Network Processor Microchip with Data Security Features
Sciencefund
1998
18 Reconfigurable Neural Processor Core
INTEL TECHNOLOGY SDN. BHD. Contract
1996
19 Public Key Crytosystem Hardware and Software
Contract
1996
20 Design of a Mixed-Mode, Testable VLSI Neuroprocessor Chip, With Built-in Current Test Sensor Structure, to be Applied in Computer Networking Hardware
Sciencefund
1996
21 ASIC Design in Digital Multimedia Hardware
INTEL TECHNOLOGY SDN. BHD. Contract
1995
22 Real Time Implementation of Image /Video Compression Algorithm Using FPGA
Short Term
1995
23 Pengujian Litar Bersepadu
INTEL TECHNOLOGY SDN. BHD. Contract
1994
24 Mikorpemprosesan Dan Pemprosesan Isyarat Digit (DSP)
Contract
1994
25 Development Of Multimedia Applications And Support Hardware For High Speed Networks
Sciencefund
1993
26 Development of Hardware and Software Analyses for Local Area Network Managements and Network Troubleshooting
Short Term
1993
27 Development of PC-based Telephone Answering System.
Short Term
1992
28 Development of Multimedia Application Sofrware and Multimedia Courseware for Faculty of Electrical Engineering
Short Term
1992
29 Development and Appplication of Artificial Intelligence (AI) in Product Diagnostics, Equipment Maintenance and Scheduling in a Semiconductor Manufacturing Plant
Short Term
1992

Legend : PUBLICATION CATEGORY TYPE OF AUTHORS

# Publication Name Year
1 Characterization Of Correlation In Stochastic Computing Functions
2ND INTERNATIONAL CONFERENCE ON ELECTRICAL, COMMUNICATION AND COMPUTER ENGINEERING
Publication In Scopus UTM FIRST AUTHOR
2020
2 Spectral-Based Convolutional Neural Network Without Multiple Spatial-Frequency Domain Switchings
NEUROCOMPUTING
Publication In Web Of Science UTM FIRST AUTHOR
2019
3 Accurate And Compact Stochastic Computations By Exploiting Correlation
TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES
Publication In Web Of Science UTM FIRST AUTHOR
2019
4 An Fpga-Based Quantum Circuit Emulation Framework Using Heisenberg Representation
INTERNATIONAL JOURNAL OF QUANTUM INFORMATION
Publication In Web Of Science UTM FIRST AUTHOR
2018
5 Paroxysmal Atrial Fibrillation Prediction Based On Hrv Analysis And Non-Dominated Sorting Genetic Algorithm Iii
COMPUTER METHODS AND PROGRAMS IN BIOMEDICINE
Publication In Web Of Science UTM FIRST AUTHOR
2018
6 Stochastic Computing Correlation Utilization In Convolutional Neural Network Basic Functions
TELKOMNIKA (TELECOMMUNICATION, COMPUTING, ELECTRONICS AND CONTROL)
Publication In Scopus UTM FIRST AUTHOR
2018
7 Algorithm To Convert Signal Interpreted Petri Net Models To Programmable Logic Controller Ladder Logic Diagram Models
INDONESIAN JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE
Publication In Scopus CO-AUTHOR
2018
8 Optimizing Fpga-Based Cnn Accelerator For Energy Efficiency With An Extended Roofline Model
TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES
Publication In Web Of Science UTM FIRST AUTHOR
2018
9 Improved Quantum Circuit Modelling Based On Heisenberg Representation
QUANTUM INFORMATION PROCESSING
Publication In Web Of Science UTM FIRST AUTHOR
2018
10 Digital Recognition Using Convolutional Neural Network
RECENT ADVANCES IN HARDWARE SOFTWARE CO DESIGN AND PATTERN RECOGNITION
Book Chapter CORRESPONDING AUTHOR
2017
11 Hardware Software Co-Simulation Of Skin Color Detection Algorithm
RECENT ADVANCES IN HARDWARE SOFTWARE CO DESIGN AND PATTERN RECOGNITION
Book Chapter CORRESPONDING AUTHOR
2017
12 Hardware Software Co-Design Of 2d Convolution System
RECENT ADVANCES IN HARDWARE SOFTWARE CO DESIGN AND PATTERN RECOGNITION
Book Chapter UTM FIRST AUTHOR
2017
13 Introduction To Quantum Computing
RECENT ADVANCES IN HARDWARE SOFTWARE CO DESIGN AND PATTERN RECOGNITION
Book Chapter CORRESPONDING AUTHOR
2017
14 An Optimized Buffer Insertion Algorithm With Delay-Power Constraints For Vlsi Layouts
TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES
Publication In Scopus CO-AUTHOR
2017
15 A Real-Time Near Infrared Image Acquisition System Based On Image Quality Assessment
JOURNAL OF REAL-TIME IMAGE PROCESSING
Publication In Web Of Science UTM FIRST AUTHOR
2017
16 An Fpga-Based Quantum Computing Emulation Framework Based On Serial-Parallel Architecture
INTERNATIONAL JOURNAL OF RECONFIGURABLE COMPUTING
Publication In Web Of Science UTM FIRST AUTHOR
2016
17 Paroxysmal Atrial Fibrillation Prediction Method With Shorter Hrv Sequences
COMPUTER METHODS AND PROGRAMS IN BIOMEDICINE
Publication In Web Of Science UTM FIRST AUTHOR
2016
18 Finger-Vein Biometric Identification Using Convolutional Neural Network
TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES
Publication In Web Of Science UTM FIRST AUTHOR
2016
19 Bounded Activation Functions For Enhanced Training Stability Of Deep Neural Networks On Visual Pattern Recognition Problems
NEUROCOMPUTING
Publication In Web Of Science UTM FIRST AUTHOR
2016
20 Gender Classi Cation: A Convolutional Neural Network Approach
TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES
Publication In Web Of Science UTM FIRST AUTHOR
2016
21 Ventricular Tachyarrhythmia Onset Prediction Based On Hrv And Genetic Algorithm
TELKOMNIKA (TELECOMMUNICATION COMPUTING ELECTRONICS AND CONTROL)
Publication In Scopus CO-AUTHOR
2016
22 Dynamic Power Dissipation Formulation For Application In Dynamic Programming Buffer Insertion Algorithm
JURNAL TEKNOLOGI (SCIENCES & ENGINEERING)
Publication In Scopus CO-AUTHOR
2016
23 Distributed B-Sdlm: Accelerating The Training Convergence Of Deep Neural Networks Through Parallelism
LECTURE NOTES IN COMPUTER SCIENCE (INCLUDING SUBSERIES LECTURE NOTES IN ARTIFICIAL INTELLIGENCE AND LECTURE NOTES IN BIOINFORMATICS)
Publication In Scopus UTM FIRST AUTHOR
2016
24 Hardware Acceleration Of A Face Detection System On Fpga
IEEE STUDENT CONF. ON RESEARCH AND DEVELOPMENT SCORED 2015
Publication In Scopus UTM FIRST AUTHOR
2016
25 An Optimized Second Order Stochastic Learning Algorithm For Neural Network Training
NEUROCOMPUTING
Publication In Web Of Science UTM FIRST AUTHOR
2016
26 A-Sdlm: An Asynchronous Stochastic Learning Algorithm For Fast Distributed Learning
13TH AUSTRALASIAN SYMPOSIUM ON PARALLEL AND DISTRIBUTED COMPUTING (AUSPDC 2015)
Publication In Scopus UTM FIRST AUTHOR
2015
27 An Optimized Second Order Stochastic Learning Algorithm For Neural Network Training
LECTURE NOTES IN COMPUTER SCIENCE
Publication In Web Of Science UTM FIRST AUTHOR
2015
28 Sleep Apnea Event Detection System Based On Heart Rate Variability Analysis
THE SECOND INTERNATIONAL CONFERENCE ON ADVANCED DATA AND INFORMATION ENGINEERING
Conference Paper UTM FIRST AUTHOR
2015
29 Microprocessor-Based Athlete Health Monitoring Device Based On Heart Rate And Stride Length Calculation
JURNAL TEKNOLOGI (D): SPECIAL ISSUE - MEDICAL SIGNAL AND IMAGES PROCESSING TECHNOLOGY
Publication In Scopus UTM FIRST AUTHOR
2015
30 Convolutional Neural Networks With Fused Layers Applied To Face Recognition
INTERNATIONAL JOURNAL OF COMPUTATIONAL INTELLIGENCE AND APPLICATIONS
Publication In Scopus UTM FIRST AUTHOR
2015
31 Generalizing Convolutional Neural Networks For Pattern Recognition Tasks
ARPN JOURNAL OF ENGINEERING AND APPLIED SCIENCES
Publication In Scopus UTM FIRST AUTHOR
2015
32 An Accurate Fpga-Based Hardware Emulation On Quantum Fourier Transform
13TH AUSTRALASIAN SYMPOSIUM ON PARALLEL AND DISTRIBUTED COMPUTING (AUSPDC 2015)
Publication In Scopus UTM FIRST AUTHOR
2015
33 An Optimization Algorithm For Simultaneous Routing And Buffer Insertion With Delay-Power Constraints In Vlsi Layout Design
15TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, ISQED 2014
Publication In Scopus CO-AUTHOR
2014
34 Hardware Implementation Of Evolvable Block-Based Neural Networks Utilizing A Cost Efficient Sigmoid-Like Activation Function
NEUROCOMPUTING
Publication In Web Of Science UTM FIRST AUTHOR
2014
35 Convolutional Neural Network For Face Recognition With Pose And Illumination Variation
INTERNATIONAL JOURNAL OF ENGINEERING AND TECHNOLOGY
Publication In Scopus UTM FIRST AUTHOR
2014
36 Optimization Of Structure And System Latency In Evolvable Block-Based Neural Networks Using Genetic Algorithm
NEUROCOMPUTING
Publication In Web Of Science UTM FIRST AUTHOR
2014
37 Hw/Sw Co-Design Of Reconfigurable Hardware-Based Genetic Algorithm In Fpgas Applicable To A Variety Of Problems
COMPUTING
Publication In Web Of Science UTM FIRST AUTHOR
2013
38 Biometric Encryption Based On A Fuzzy Vault Scheme With A Fast Chaff Generation Algorithm
FUTURE GENERATION COMPUTER SYSTEMS-THE INTERNATIONAL JOURNAL OF GRID COMPUTING AND ESCIENCE
Publication In Web Of Science CORRESPONDING AUTHOR
2013
39 A Two-Step Binary Particle Swarm Optimization Approach For Routing In Vlsi
ICIC EXPRESS LETTERS (ICIC-EL)
Publication In Scopus CO-AUTHOR
2012
40 A Network-On-Chip Simulation Framework For Homogeneous Multi-Processor System-On-Chip
PROCEEDINGS OF INTERNATIONAL CONFERENCE ON ASIC
Publication In Scopus CO-AUTHOR
2011
41 A Tightly Coupled Hardware For Fpga-Based Embedded Elliptic Curve Cryptosystem In Gf(2m)
International Graduate Conference on Engineering and Science (IGCES) 2008
Conference Paper INDIVIDUAL AUTHOR
2008
42 Optimal Routing Algorithm For Minimizing Interconnect Delay In Vlsi Layout Design
Int. Conf. on Robotic, Vision, Information and Signal Processing (ROVISP 2007)
Conference Paper INDIVIDUAL AUTHOR
2007
43 Embedded Cryptosystem For Strong Data Security In Telemedicine
International Conference on Robotic, Vision, Information and Signal Processing (ROVISP 2007)
Conference Paper INDIVIDUAL AUTHOR
2007
44 Cryptographic Hardware Implementation In An Ip-Based System-On-Chip(Soc)
IP Based Electronic System Conference & Exhibition
Conference Paper INDIVIDUAL AUTHOR
2007
45 System Level Modelling Of Compressed Memory Architecture Using Systemc
Proceedings of the International Conference on Robotics,Vision, Information and Signal Processing,ROVISP'08
Conference Paper INDIVIDUAL AUTHOR
2007
46 Electronic System Level (Esl) Design Methodology For Ip-Based System-On-Chip (Soc)
International Conference on Robotic, Vision, Information and Signal Processing (ROVISP 2007)
Conference Paper INDIVIDUAL AUTHOR
2007
47 A Cryptographic Service Provider (Csp) For An Fpga-Based Cryptohardware System
Regional Conference on Computational Science and Technology (RCCT-2007)
Conference Paper INDIVIDUAL AUTHOR
2007

Legend : SUPERVISION LEVEL LEVEL OF STUDY STATUS

# Supervision List
1 NAZAR ELFADIL M A ELGAZOLI

SUPERVISOR PHD ON GOING
2 SHAIKH NASIR @ NASIR BIN SHAIKH HUSIN
OPTIMIZATION OF ROUTING ALGORITHM FOR INTERCONNECT DELAY IN ULTRA LARGE SCALE INTEGRATION DESIGNS
SUPERVISOR PHD GRADUATED
3 HAU YUAN WEN
SYSTEMC - BASED DESIGN FRAMEWORK FOR AN EMBEDDED SYSTEM IMPLEMENTED AS SYSTEM-ON-CHIP
SUPERVISOR PHD GRADUATED
4 RABIA BAKHTERI D/O JAHANGIR BAKHTERI
A BIOMETRIC ENCRYPTION SYSTEM ALGORITHM DEVELOPMENT AND SYSTEM LEVEL DESIGN
SUPERVISOR PHD GRADUATED
5 VISHNU A/L PARAMASIVAM
AN EVOLVABLE BLOCK-BASED NEURAL NETWORK ARCHITECTURE FOR EMBEDDED HARDWARE
SUPERVISOR PHD GRADUATED
6 SYAFEEZA BINTI AHMAD RADZI
CONVOLUTIONAL NEURAL NETWORKS FOR FACE RECOGNITION AND FINGER-VEIN BIOMETRIC IDENTIFICATION
SUPERVISOR PHD GRADUATED
7 LIEW SHAN SUNG
AN EFFICIENT AND EFFECTIVE CONVOLUTIONAL NEURAL NETWORK FOR VISUAL PATTERN RECOGNITION
SUPERVISOR PHD GRADUATED
8 LEE YEE HUI
QUANTUM COMPUTING MODELLING ON FIELD PROGRAMMABLE GATE ARRAY BASED ON STATE VECTOR AND HEISENBERG MODELS
SUPERVISOR PHD GRADUATED
9 BOON KHANG HUA
AN OPTIMIZATION METHOD BASED ON GENETIC ALGORITHM FOR HEART RATE VARIABILITY ANALYSIS IN THE PREDICTION OF THE ONSET OF CARDIAC ARRHYTHMIA
SUPERVISOR PHD GRADUATED
10 ZULFAKAR BIN ASPAR
PETRI NET MODELLING OF PROGRAMMABLE LOGIC CONTROLLER
SUPERVISOR PHD GRADUATED
11 HAMDAN USAMAH HAMDAN ABDELLATEF
STOCHASTIC COMPUTING SYSTEM HARDWARE DESIGN FOR CONVOLUTIONAL NEURAL NETWORKS OPTIMIZED FOR ACCURACY, AREA AND ENERGY EFFICIENCY
SUPERVISOR PHD GRADUATED
12 SAYED OMID AYAT
ENERGY-EFFICIENT SPECTRAL CONVOLUTIONAL NEURAL NETWORK ACCELERATOR ON FIELD-PROGRAMMABLE GATE ARRAY
SUPERVISOR PHD GRADUATED
13 SHAHRIYAR MASUD RIZVI
A LOW-COMPLEXITY COMPLEX-VALUED ACTIVATION FUNCTION FOR FAST AND ACCURATE SPECTRAL DOMAIN CONVOLUTIONAL NEURAL NETWORK
CO-SUPERVISOR PHD ON GOING
14 CHONG WEI SHENG
DESIGN OF A HASH PROCESSOR CHIP AND THE EMPLEMENTATION OF A DIGITAL SIGNATURE SUBSYSTEM FOR DATA SECURITY
SUPERVISOR MASTER GRADUATED
15 CHEANG CHOEN HOE

SUPERVISOR MASTER ON GOING
16 SURESH BABU A/L SUBRAMANIAM

SUPERVISOR MASTER ON GOING
17 TEOH GIAP SENG

SUPERVISOR MASTER ON GOING
18 YEEM KAH MENG

SUPERVISOR MASTER END OF STUDY PERIOD
19 TEH J-WING

SUPERVISOR MASTER GRADUATED
20 LIM KIE WOON

SUPERVISOR MASTER GRADUATED
21 SYAFEEZA BINTI AHMAD RADZI
CONVOLUTIONAL NEURAL NETWORKS FOR FACE RECOGNITION AND FINGER-VEIN BIOMETRIC IDENTIFICATION
SUPERVISOR MASTER GRADUATED
22 HAU YUAN WEN
SYSTEMC - BASED DESIGN FRAMEWORK FOR AN EMBEDDED SYSTEM IMPLEMENTED AS SYSTEM-ON-CHIP
SUPERVISOR MASTER GRADUATED
23 AVINASH A/L RAJAH
VLSI OF A NEUROHARDWARE PROCESSOR IMPLEMENTING THE KOHONEN NEURAL NETWORK ALGORITHM
SUPERVISOR MASTER GRADUATED
24 ARUL A/L PANIANDI
A HARDWARE IMPLEMENTATION OF RIVEST-SHAMIR-ADLEMAN CO-PROCESSOR FOR RESOURCE CONSTRAINED EMBEDDED SYSTEMS
SUPERVISOR MASTER GRADUATED
25 MOHD IZUAN BIN ISMAIL
DESIGN OF AN ADVANCED ENCRYPTION STANDARD CRYPTO - PROCESSOR CORE FOR FIELD PROGRAMMABLE GATE ARRAY IMPLEMENTATION
SUPERVISOR MASTER GRADUATED
26 ILLIASAAK AHMAD
A CUSTOMIZABLE CRYPTOGRAPHIC SERVICE PROVIDER FOR AN EMBEDDED CRYPTOHARDWARE SYSTEM
SUPERVISOR MASTER GRADUATED
27 CH'NG HENG SUN
A HARDWARE CO-PROCESSOR IN FPGA FOR HIGH SPEED COMPUTATION OF SHORTEST PATH GRAPH ALGORITHM
SUPERVISOR MASTER GRADUATED
28 NORASHIKIN BT M THAMRIN
A FIELD PROGRAMMABLE GATE ARRAY-BASED CRYTOGRAPHIC SYSTEM-ON-CHIP
SUPERVISOR MASTER GRADUATED
29 RABIA BAKHTERI D/O JAHANGIR BAKHTERI

SUPERVISOR MASTER GRADUATED
30 CHEW EIK WEE
A COMPUTER AIDED DESIGN SOFTWARE MODULE FOR CLOCK TREE SYNTHESIS IN VERY LARGE SCALE INTEGRATION DESIGN
SUPERVISOR MASTER GRADUATED
31 VISHNU A/L PARAMASIVAM

SUPERVISOR MASTER GRADUATED
32 MOHD NAZRIN BIN MOHD YASSIN
IMPLEMNTATION OF BIOMETRIC SYSTEMS IN FPGA-BASED HARDWARE PLATFORM.
SUPERVISOR MASTER GRADUATED
33 ARIF IRWANSYAH
FPGA IMPLEMENTATION OF ELLIPTIC CURVE CRYPTOGRAPHY OVER GF(P) WITH RESIDUE NUMBER SYSTEMS
SUPERVISOR MASTER GRADUATED
34 ENG PEI CHEE
FINGER-VEIN BIOMETRIC AUTHENTICATION IN A SYSTEM-ON-CHIP DESIGN BASED ON FIELD PROGRAMMABLE GATE ARRAYS
SUPERVISOR MASTER GRADUATED
35 LIEW TEK YEE
HARDWARE-BASED BIOMETRIC ENCRYPTION IMPLEMENTATION WITH GAUSS-JORDAN ALGORITHM ACCELERATOR CORE IN FIELD PROGRAMMABLE GATE ARRAYS
SUPERVISOR MASTER GRADUATED
36 SATHIVELLU A/L BALAKRISHNAN
HARDWARE-BASED GENETIC ALGORITHM IMPLEMENTATION IN FIELD PROGRAMMABLE GATE ARRAYS
SUPERVISOR MASTER GRADUATED
37 MOHD ANNUAR BIN SUHAINI
FINGER-BASED MULTIMODAL BIOMETRICS SYSTEM IN FIELD PROGRAMMABLE GATE ARRAY
SUPERVISOR MASTER GRADUATED
38 LEE YEE HUI
A QUANTUM COMPUTING MODEL FOR FIELD PROGRAMMABLE GATE ARRAY TECHNOLOGY
SUPERVISOR MASTER GRADUATED
39 MOGANESHWARAN S/O RAJASEGARAN
FINGERPRINT-FINGERVEIN MULTIMODAL BIOMETRIC AUTHENTICATION SYSTEM IN FIELD PROGRAMMABLE GATE ARRAY HARDWARE
SUPERVISOR MASTER GRADUATED
40 JOHNNY KONG JAK KAN
SOFTWARE AND HARDWARE CO SIMULATION USING SYSTEM VERILOG DPI PLATFORM FOR IMAGE PROCESSING
SUPERVISOR MASTER GRADUATED
41 IBRAHIM ISA

SUPERVISOR MASTER GRADUATED
42 NGO WAI LOON

SUPERVISOR MASTER GRADUATED
43 NUHAIRI BIN ANUAR

SUPERVISOR MASTER GRADUATED
44 WONG XUE YUAN

SUPERVISOR MASTER GRADUATED
45 MOHAMAD AMIN BIN NOORDIN

SUPERVISOR MASTER GRADUATED
46 VIDYA DHARAN A/L SRI DARAN NAMBIAR
A FACE RECOGNITION SYSTEM ACCELERATED ON EMBEDDED GRAPHICS PROCESSING UNIT ENABLED BY COMPUTE UNIFIED DEVICE ARCHITECTURE
SUPERVISOR MASTER GRADUATED
47 YEAP HAN CHIEN
FACE DETECTION HARDWARE ACCELERATOR USING C-BASED HIGH-LEVEL SYNTHESIS
SUPERVISOR MASTER GRADUATED

Grant (PI)

INDUSTRY GRANTS
1
INTERNATIONAL GRANTS
2
NATIONAL GRANTS
9
UNIVERSITY FUND
2
TOTAL

Publications

INDEXED PUBLICATION
35
NON-INDEXED PUBLICATION
0
OTHERS PUBLICATION
12
TOTAL

Supervision

DEGREE
0
MASTER
34
PHD
13
TOTAL