GRANT (PI & MEMBERS)

24

PUBLICATIONS

49

INDEXED PUBLICATIONS

35

H-INDEXED (SCOPUS)

CITATIONS (SCOPUS)

TOTAL STUDENTS

Grant (PI)

INDUSTRY GRANTS
2
NATIONAL GRANTS
4
UNIVERSITY FUND
7
TOTAL

Publications

INDEXED PUBLICATION
35
NON-INDEXED PUBLICATION
3
OTHERS PUBLICATION
11
TOTAL

Supervisions

DEGREE
0
MASTER
17
PHD
11
TOTAL

Legend : SPONSOR TYPE OF GRANT

Grant Name Year
Hybrid of BIST and Non Scan Design for Testability Method at Register Transfer Level
RUG OF UTM UTM Encouragement Research
2019
STATISTICAL ASSOCIATION OF TONGUE CHARACTERISTICS OF PERSON DESCRIBED USING ORIENTAL MEDICINE PRACTICES AND THEIR CORRESPONDEDING ALLOPATHIC HEALTH STATUS
MINISTRY OF EDUCATION Networking Grant
2019
FPGA Prototype Development and Pre-Clinical Evaluation of Intelligent Electrocardiogram Monitoring Device for Early Heart Disease Detection and Prevention
MINISTRY OF EDUCATION Prototype Development Research Grant Scheme
2019
COMPUTER AIDED DETECTION/DIAGNOSIS OF LIVER PATHOLOGIES USING CT IMAGES FOR TREATMENT PLANNING AND MONITORING OF LIVER CANCER PATIENTS
RUG OF UTM Professional Development Research University
2019
Hardware Acceleration for Extreme Learning Machine on Smart Chip FPGA
RUG OF UTM Tier 2
2018
Hybrid Reconfigurable Transmitting Power and Adaptive Packet Relocator Scheme in Wireless Network-on-Chip
RUG OF UTM Potential Academic Staff
2017
HARDWARE ACCELERATION OF EFFICIENT TONGUE DIAGNOSIS DEVICE
RUG OF UTM Tier 1
2017
A Novel and Smart Arrhythmia Analyzer Design based on Enhanced Artificial Intelligence Algorithm for Cardiac Home Monitoring
MINISTRY OF EDUCATION Transdiscplinary Research Grant Scheme
2016
BUILT-IN SELF-TEST FOR FUNCTIONAL REGISTER-TRANSFER-LEVEL DESIGN USING ASSIGNMENT DECISION DIAGRAM
RUG OF UTM Encouragement Grant
2015
Fundamental Study of Finite-State-Machine with Data Path for Power-Aware Three-Dimensional Integrated Circuits
MINISTRY OF EDUCATION Fundamental Research Grant Scheme
2014
LOW-POWER DEPENDABLE SYSTEM-ON-CHIP FOR MPEG4 PROCESSING
RUG OF UTM Tier 1
2014
Web-based Telecardiology Development for UTM Pilot Case Study
RUG OF UTM Flagship
2014
HARDWARE - FPGA BASED ENABLED CONSTRAINT RANDOM VALIDATION (CRV)
COLLABORATIVE RESEARCH IN ENGINEERING, SCIENCE & TECHNOLOGY CENTER (CREST) Others
2014
Multiprocessor System-On-Chip Based On Low Latency Network-On-Chip For High-Throughput Traffic Classification On NetFPGA
MINISTRY OF EDUCATION Fundamental Research Grant Scheme
2013
STUDY OF INDUSTRY LEADING ATE (AUTOMATED TEST EQUIPMENT) AND ENABLING A TOTAL TEST - PLATFORM SOLUTION FOR ALTERA'S PRODUCTION TESTING
COLLABORATIVE RESEARCH IN ENGINEERING, SCIENCE & TECHNOLOGY CENTER (CREST) Others
2013
A Design Framework for Multi-Processor System-on-Chip (MPSoC)Architecture Design-Space Exploration in Biomedical Application: Human Heart ECG Monitoring and Processing
Sciencefund
2013
Technology Exploration of On-Line Cardiac Monitoring and Diagnostic Medical Device in Telecardiology
RUG OF UTM Flagship
2013
Parameterized Thermal Simulator for Temperature-Aware Testing Methodology
Tier 2
2012
Adaptive Online Testing For MPEG Processing On Network-On-Chip
Sciencefund
2012
Multi-Constrained System-on-Chip (SoC) Test Planning Framework based on Enhanced 3-D Floorplanning
RUG OF UTM Tier 2
2011
A Dependable System-on-Chip Architecture for Image Processing
UNIVERSITI TEKNOLOGI MALAYSIA UTM R&D Fund
2011
A New Design-For_testability (DFT) Technique for a System-on-Chip (Soc)
UNIVERSITI TEKNOLOGI MALAYSIA Fund Without Provision
2008
Development of High-Level Design-for-Testability Method and Digital Testing System for Education.
Sciencefund
2008
High Level Design Design for Testability Method for Assignment Decision Diagram
UNIVERSITI TEKNOLOGI MALAYSIA Institutional Research Grant Scheme
2008

Legend : PUBLICATION CATEGORY TYPE OF AUTHORS

Publication Name Year
Fpga-Assisted Assertion-Based Verification Platform
JOURNAL OF TELECOMMUNICATION, ELECTRONIC AND COMPUTER ENGINEERING (JTEC)
Journal Article Non Citation-Indexed UTM FIRST AUTHOR
2020
A Review Of Breast Boundary And Pectoral Muscle Segmentation Methods In Computer-Aided Detection/Diagnosis Of Breast Mammography
ARTIFICIAL INTELLIGENCE REVIEW
Publication In Web Of Science UTM FIRST AUTHOR
2020
Register-Transfer-Level Features For Machine-Learning-Based Hardware Trojan Detection
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS, COMMUNICATIONS AND COMPUTER SCIENCES
Publication In Web Of Science CORRESPONDING AUTHOR
2020
Accelerating Extreme Learning Machine On Fpga By Hardware Implementation Of Given Rotation - Qrd
INTERNATIONAL JOURNAL OF INTEGRATED ENGINEERING
Publication In Scopus CO-AUTHOR
2019
Review Of Machine Learning Based Hardware Trojan Detection Methods
DEFENCE S AND T TECHNICAL BULLETIN
Publication In Scopus UTM FIRST AUTHOR
2019
Classification Of Trojan Nets Based On Scoap Values Using Supervised Learning
2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
Publication In Web Of Science UTM FIRST AUTHOR
2019
Performance Comparison Of Colour Correction And Colour Grading Algorithm For Medical Imaging Applications
INTERNATIONAL CONFERENCE ON ELECTRIC, ELECTRONIC & COMPUTER ENGINEERING: INTCEECE 2018
Proceedings CO-AUTHOR
2018
Hpfog: A Fpga-Based Fog Computing Platform
NETWORKING, ARCHITECTURE, AND STORAGE (NAS), 2017 INTERNATIONAL CONFERENCE ON
Publication In Scopus CO-AUTHOR
2017
Hardware Transactional Memory Architecture With Adaptive Version Management For Multi-Processor Fpga Platforms
JOURNAL OF SYSTEMS ARCHITECTURE
Publication In Web Of Science CO-AUTHOR
2017
Integrated Low-Power Gating Scan Cell For Test Power Minimization
ADVANCES IN MICROELECTRONICS: REVIEWS
Book Chapter UTM FIRST AUTHOR
2017
The Design And Implementation Of A Low-Power Gating Scan Element In 32/28 Nm Cmos Technology
JOURNAL OF LOW POWER ELECTRONICS AND APPLICATIONS
Publication In Scopus CORRESPONDING AUTHOR
2017
Small Area Implementation For Optically Reconfigurable Gate Array Vlsi: Fft Case
JOURNAL OF SCIENCE & INDUSTRY RESEARCH
Publication In Web Of Science CO-AUTHOR
2017
Test Register Insertion At Rtl Based On Reduced Bist
JURNAL TEKNOLOGI
Publication In Web Of Science CO-AUTHOR
2017
A Fast Svm-Based Tongue'S Colour Classification Aided By K-Means Clustering Identifiers And Colour Attributes As Computer-Assisted Tool For Tongue Diagnosis
JOURNAL OF HEALTHCARE ENGINEERING
Publication In Web Of Science UTM FIRST AUTHOR
2017
An Integrated Dft Solution For Power Reduction In Scan Test Applications By Low Power Gating Scan Cell
INTEGRATION, THE VLSI JOURNAL
Publication In Web Of Science CORRESPONDING AUTHOR
2017
Ping-Lock Round Robin Arbiter
MICROELECTRONICS JOURNAL
Publication In Web Of Science CO-AUTHOR
2017
A Customized Reconfiguration Controller With Remote Direct Icap Access For Dynamically Reconfigurable Platform
TELKOMNIKA (TELECOMMUNICATION, COMPUTING, ELECTRONICS AND CONTROL)
Publication In Scopus CO-AUTHOR
2017
Quantification Of Tongue Colour Using Machine Learning In Kampo Medicine
EUROPEAN JOURNAL OF INTEGRATIVE MEDICINE
Publication In Web Of Science UTM FIRST AUTHOR
2016
Power-Aware Through-Silicon-Via Minimization By Partitioning Finite State Machine With Datapath
PROCEEDINGS - IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS
Publication In Scopus UTM FIRST AUTHOR
2016
Sva Checker Generator For Fpga-Based Verification Platform
2016 IEEE International Symposium on Circuits and Systems (ISCAS)
Publication In Scopus UTM FIRST AUTHOR
2016
Improved Flow Control For Minimal Fully Adaptive Routing In 2d Mesh Noc
9TH INTERNATIONAL WORKSHOP ON NETWORK ON CHIP ARCHITECTURES (NOCARC)
Publication In Web Of Science UTM FIRST AUTHOR
2016
A Modular Architecture For Dynamically Reconfigurable Middlebox With Customized Reconfiguration Handler
PROCEEDINGS OF THE 2016 FIELD-PROGRAMMABLE TECHNOLOGY (FPT 2016)
Conference Paper CO-AUTHOR
2016
Tongue'S Substance And Coating Recognition Analysis Using Hsv Color Threshold In Tongue Diagnosis
THE 1ST INTERNATIONAL WORKSHOP ON PATTERN RECOGNITION
Conference Paper CORRESPONDING AUTHOR
2016
A Fast And Effective Segmentation Algorithm With Automatic Removal Of Ineffective Features On Tongue Images
JURNAL TEKNOLOGI
Publication In Scopus CORRESPONDING AUTHOR
2016
A Closed-Loop Power Manager For Transmission Power Control In Wireless Network-On-Chip Architecture
JURNAL TEKNOLOGI
Publication In Scopus CO-AUTHOR
2015
Virtual Channel And Switch Allocation For Low Latency Network-On-Chip Routers
2015 IEEE 23RD ANNUAL INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, FCCM 2015
Publication In Scopus CO-AUTHOR
2015
Low Latency Network-On-Chip Router Microarchitecture Using Request Masking Technique
INTERNATIONAL JOURNAL OF RECONFIGURABLE COMPUTING
Publication In Scopus UTM FIRST AUTHOR
2015
Comparative Study Of Electrocardiogram Qrs Complex Detection Algorithm On Field Programmable Gate Array Platform
2014 IEEE CONFERENCE ON BIOMEDICAL ENGINEERING AND SCIENCES (IECBES 2014)
Publication In Scopus CO-AUTHOR
2015
Built-In Self Test Power And Test Time Analysis In On-Chip Networks
CIRCUITS SYSTEMS AND SIGNAL PROCESSING
Publication In Web Of Science UTM FIRST AUTHOR
2015
Development Of Platform-Independent Web-Based Telecardiology Application For Pilot Case Study
2014 IEEE CONFERENCE ON BIOMEDICAL ENGINEERING AND SCIENCES (IECBES 2014)
Publication In Scopus CO-AUTHOR
2015
Adaptive Configurable Transactional Memory For Multi-Processor Fpga Platforms
2015 IEEE 23RD ANNUAL INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, FCCM 2015
Publication In Scopus CO-AUTHOR
2015
A Novel Scan Architecture For Low Power Scan-Based Testing
VLSI DESIGN
Publication In Scopus UTM FIRST AUTHOR
2015
Configurable Version Management Hardware Transactional Memory For Multi-Processor Platform
THE 2014 IAES INTERNATIONAL CONFERENCE ON ELECTRICAL ENGINEERING, COMPUTER SCIENCE AND INFORMATICS (EECSI 2014)
Proceedings CO-AUTHOR
2014
Rrbox: A Remote Dynamically Reconfigurable Middlebox For Network Protection
THE SECOND INTERNATIONAL SYMPOSIUM ON COMPUTING AND NETWORKING
Proceedings CO-AUTHOR
2014
Remote Dynamically Reconfigurable Platform Using Netfpga
PROCEEDINGS - IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS
Publication In Scopus UTM FIRST AUTHOR
2014
Hardware Transactional Memory On Multi-Processor Fpga Platform
THE IEEE INTERNATIONAL SYMPOSIUM ON CIRCUIT AND SYSTEMS 2014 (ISCAS’2014)
Publication In Scopus CO-AUTHOR
2014
Packet Logging Mechanism For Adaptive Online Fault Detection On Network-On-Chip
PROCEEDINGS - IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS
Publication In Scopus CO-AUTHOR
2014
Study On Test Compaction In High-Level Automatic Test Pattern Generation (Atpg) Platform
CIRCUITS & SYSTEMS
Journal Article Non Citation-Indexed UTM FIRST AUTHOR
2013
Feasible Transition Path Generation For Efsm-Based System Testing
IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS
Publication In Web Of Science UTM FIRST AUTHOR
2013
A Semi-Analytical Approach To Study The Energy Consumption Of On-Chip Networks Testing
JOURNAL OF LOW POWER ELECTRONICS
Publication In Scopus UTM FIRST AUTHOR
2013
Built-In Self-Test For Functional Register-Transfer Level Using Assignment Decision Diagram
PROCEEDINGS OF THE IEEE TWELFTH INTERNATIONAL WORKSHOP ON RTL AND HIGH LEVEL TESTING (WRTLT'11)
Proceedings CO-AUTHOR
2011
A New Design-For-Testability Method Based On Thru-Testability
Journal of Electronic Testing-Theory and Applications
Publication In Web Of Science CORRESPONDING AUTHOR
2011
A Network-On-Chip Simulation Framework For Homogeneous Multi-Processor System-On-Chip
PROCEEDINGS OF INTERNATIONAL CONFERENCE ON ASIC
Publication In Scopus CO-AUTHOR
2011
A New Class Of Easily Testable Assignment Decision Diagrams
MALAYSIAN JOURNAL OF COMPUTER SCIENCE
Publication In Web Of Science CO-AUTHOR
2010
A Nonscan Design-For-Testability Method For Register-Transfer-Level Circuits To Guarantee Linear-Depth Time Expansion Models
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Conference Paper INDIVIDUAL AUTHOR
2008
Design For Testability Ii: From High Level Perspective
ADVANCES IN MOCROELECTRONICS
Book Chapter CO-AUTHOR
2008
A New Class Of Easily Testable Assignment Decision Diagrams
9th International Workshop on RTL and High Level Testing
Conference Paper INDIVIDUAL AUTHOR
2008
Analysis Of Test Generation Complexity For Stuck-At And Path Delay Faults Based On ¿K-Notation
IEICE Transaction on Information and Systems
Journal Article Non Citation-Indexed INDIVIDUAL AUTHOR
2007
An Extended Class Of Acyclically Testable Circuits
IEEE 8th Workshop on RTL and High Level Testing
Conference Paper INDIVIDUAL AUTHOR
2007
Supervision List
NORLINA BINTI PARAMAN
CO-SUPERVISOR
201620171 DESIGN FOR TESTABILITY METHOD AT REGISTER TRANSFER LEVEL PHD
ALIREZA MONEMI
CO-SUPERVISOR
201620171 AN ENHANCED LOW LATENCY NETWORK-ON-CHIP ROUTER OPTIMIZED FOR PROTOTYPING ON FIELD PROGRAMMABLE GATE ARRAY PHD
MAHSHID MOJTABAVI NAEINI
SUPERVISOR
201620172 POWER MINIMIZATION FOR SCAN-BASED TESTING USING LOW-POWER INTEGRATED DESIGN-FOR-TESTABILITY PHD
NUR DIYANA BINTI KAMARUDIN
SUPERVISOR
201620172 TONGUE DISEASE DIAGNOSIS BASED ON BRIGHTNESS CONFORMABLE MULTIPLIER THRESHOLDING AND K-MEANS SUPPORT VECTOR MACHINE CLASSIFIER PHD
HASLIZA BINTI HASSAN
SUPERVISOR
201720181 THERMAL SAFE SYSTEM-ON-CHIP TEST SCHEDULING USING DYNAMIC VOLTAGE AND FREQUENCY SCALING PHD
MAHDIEH NADISENEJANI
CO-SUPERVISOR
201720182 PHD
ILI SHAIRAH BINTI ABDUL HALIM
CO-SUPERVISOR
202020212 ANALYSIS AND ENHANCEMENT OF OPTICALLY RECONFIGURABLE GATE ARRAY CHIP RELIABILITY   PHD
TAN TZE HON
CO-SUPERVISOR
202020212 AN FPGA-BASED FOG NODE ARCHITECTURE WITH RECONFIGURABLE APPLICATION PLANE PHD
AYUB CHIN ABDULLAH
SUPERVISOR
202020212 POWER-AWARE THROUGH-SILICON-VIA MINIMIZATION USING FINITE STATE MACHINE WITH DATAPATH PARTITIONING PHD
CHOO HAU SIM
SUPERVISOR
202020212 REGISTER-TRANSFER-LEVEL HARDWARE TROJAN DETECTION BASED ON SUPERVISED MACHINE LEARNING AND MULTIPLE-ABSTRACTION-LEVEL FEATURES PHD
NORLINA BINTI PARAMAN
CO-SUPERVISOR
200520061 A NEW DESIGN-FOR-TESTABILITY METHOD AT HIGH-LEVEL USING ASSIGNMENT DECISION DIAGRAM MASTER
AYUB CHIN ABDULLAH
SUPERVISOR
201220132 POWER-AWARE THROUGH-SILICON-VIA MINIMIZATION USING FINITE STATE MACHINE WITH DATAPATH PARTITIONING MASTER
TAN TZE HON
CO-SUPERVISOR
201420151 AN FPGA-BASED FOG NODE ARCHITECTURE WITH RECONFIGURABLE APPLICATION PLANE MASTER
JEEVAN A/L SIRKUNAN
CO-SUPERVISOR
201420152 INTERLEAVED INCREMENTAL SUPPORT VECTOR MACHINEFOR EMBEDDED APPLICATIONS MASTER
KHEW HE XIANG
SUPERVISOR
201620172 TEST PROGRAM MIGRATION FROM A PROPRIETY TEST SYSTEM TO AUTOMATED TEST EQUIPMENT MASTER
NURITA BINTI MOHAMAD
SUPERVISOR
201720181 ACCELERATION OF ASSERTATION-BASED VERIFICATION USING FIELD PROGRAMMABLE GATE ARRAY MASTER
LIM THOL YONG
CO-SUPERVISOR
201720182 ENHANCED LOCALIZATION WITH ADAPTIVE NORMAL DISTRIBUTION TRANSFORM MONTE CARLO LOCALIZATION FOR MAP BASED NAVIGATION ROBOT MASTER
MAHDIEH NADISENEJANI
CO-SUPERVISOR
201820191 ARCHITECTURE-LEVEL POWER-TIME-AREA ESTIMATORS FOR IEEE 1149.1 STRUCTURE IN TESTING INTERCONNECT RESOURCES OF NETWORK-ON-CHIP MASTER
AOI UEDA
SUPERVISOR
201920201 MASTER
JION HIROSE
SUPERVISOR
201920201 MASTER
TAN CHONG YEAM
SUPERVISOR
201920201 ALGORITHM RESTRUCTURING AND DIRECTIVES CONFIGURATION OF HIGH-LEVEL SYNTHESIS TOWARDS HIGH-PERFOMANCE EXTREME LEARNING MACHINE ACCELERATOR MASTER
KOK CHEE HOO
SUPERVISOR
201920201 GATE-LEVEL HARDWARE TROJAN DETECTION BASED ON TESTABILITY MEASURES AND NETLIST STRUTURAL FEATURES MASTER
SARAVID A/L SUCHAAD
SUPERVISOR
202020212 IMPLEMENTATION OF BLOCKCHAIN ON HOME AUTOMATION FOR PRIVACY MASTER
KHAIRUL SHAZWAN BIN MAMAT
SUPERVISOR
202020212 PHYSICAL UNCLONABLE FUNCTION DESIGN FOR SECURE SCAN CHAIN MASTER
MOHAMAD HAFIZAT BIN ZAINAL ABIDIN
SUPERVISOR
202020212 SCALABLE BLOCKCHAIN ARCHITECTURE FOR VEHICULAR NETWORK MASTER
AHMAD AWALLUDDIN BIN MOHD GHAZALI
SUPERVISOR
202020212 LOW POWER SCAN CHAIN WRAPPER BASED ONINTEGRATED LOW POWER GATING (ILPG) SCAN CELL MASTER