NORLINA BINTI PARAMAN

PENSYARAH KANAN (DS52)

Grant

9

Publication

30

Indexed Publication

5

H-Index (SCOPUS)

Citations (SCOPUS)

Note: List of all research grants and publications shown are based on data registered in RADIS

About Me

pnorlina@utm.my

FACULTY OF ENGINEERING

INNOVATIVE ENGINEERING

HIGH LEVEL VERIFICATION; IC TEST; DESIGN FOR TEST; PROGRAMMING LANGUAGES

# Grant Name Year
1 Hybrid of BIST and Non Scan Design for Testability Method at Register Transfer Level
RUG OF UTM UTM Encouragement Research
2019
2 TRAFFIC FLOWS CLASSIFICATION USING MACHINE LEARNING TECHNIQUES TO CONTROL CHILDREN'S ONLINE ACTIVITY
RUG OF UTM Tier 2
2019
3 Obfuscated Computer Virus Detection using Machine Learning Algorithm
RUG OF UTM Tier 2
2018
4 HARDWARE ACCELERATION OF EFFICIENT TONGUE DIAGNOSIS DEVICE
RUG OF UTM Tier 1
2017
5 A SIMULATION STUDY ON QUANTUM EFFECT IN TWIN SILICON NANOWIRE FIELD-EFFECT TRANSISTOR
RUG OF UTM Tier 2
2017
6 Innovative Arduino hardware development and programming for Sekolah Tun Fatimah and SMK Bandar Tenggara students
SEAGATE INTERNATIONAL (JOHOR) SDN. BHD. Networking Grant
2017
7 BUILT-IN SELF-TEST FOR FUNCTIONAL REGISTER-TRANSFER-LEVEL DESIGN USING ASSIGNMENT DECISION DIAGRAM
RUG OF UTM Encouragement Grant
2015
8 EVASION MALWARE DETECTION USING MACHINE LEARNING WITH KNOWN SIGNATURES ON NETWORK NODES
RUG OF UTM Potential Academic Staff
2014
9 Parameterized Thermal Simulator for Temperature-Aware Testing Methodology
Tier 2
2012

# Publication Name Year
1 Fpga-Assisted Assertion-Based Verification Platform
JOURNAL OF TELECOMMUNICATION, ELECTRONIC AND COMPUTER ENGINEERING (JTEC)
Journal Article Non Citation-Indexed CORRESPONDING AUTHOR
2020
2 Multiple Controlled Antirandom Testing (Mcat) For High Fault Coverage In A Black Box Environment
IEEE ACCESS
Publication In Web Of Science CO-AUTHOR
2019
3 Impact Of Device Parameter Variation On The Electrical Characteristic Of N-Type Junctionless Nanowire Transistor With High-K Dielectrics
4TH INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONIC, COMMUNICATION AND CONTROL ENGINEERING 2019
Proceedings CO-AUTHOR
2019
4 Development Of Testability Measures For Combinational Logic Circuit
PROCEEDING OF 2019 ELECTRICAL ENGINEERING SYMPOSIUM (EES2019)
Proceedings UTM FIRST AUTHOR
2019
5 Testability Method At Register Transfer Level And Gate Level
PROCEEDING OF 2019 ELECTRICAL ENGINEERING SYMPOSIUM (EES2019)
Proceedings UTM FIRST AUTHOR
2019
6 Reliability Of Graphene As Charge Storage Layer In Floating Gate Flash Memory
INDONESIAN JOURNAL OF ELECTRICAL ENGINEERING AND INFORMATICS (IJEEI)
Publication In Scopus CO-AUTHOR
2019
7
A SIMULATION STUDY ON QUANTUM EFFECT IN TWIN SILICON NANOWIRE FIELD-EFFECT TRANSISTOR
Clasified/Technical Report CORRESPONDING AUTHOR
2018
8 Horizontal Diversity In Test Generation For High Fault Coverage
TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES
Publication In Web Of Science CO-AUTHOR
2018
9 Rapid Prototyping Of Noc-Based Mpsoc Based On Dataflow Modeling Of Real-World Applications
2018 9TH IEEE CONTROL AND SYSTEM GRADUATE RESEARCH COLLOQUIUM
Conference Paper CO-AUTHOR
2018
10 Implementation Of Misr On Greater Commun Divisor Circuit
PROCEEDINGS OF 2018 ELECTRICAL ENGINEERING SYMPOSIUM (EES2018)
Proceedings UTM FIRST AUTHOR
2018
11 Graphene As Charge Storage Layer In Floating Gate Flash Memory: Comparison Between N-Channel And P-Channel
3RD INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONIC, COMMUNICATION AND CONTROL ENGINEERING (ICEECC 2018)
Proceedings CO-AUTHOR
2018
12 Development Of Fault Simulator On Automatic Test Pattern Generation
PROCEEDINGS OF 2018 ELECTRICAL ENGINEERING SYMPOSIUM (EES2018)
Proceedings UTM FIRST AUTHOR
2018
13 Machine Vision Based Smart Parking System Using Internet Of Things
2018 INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONIC, COMMUNICATION AND CONTROL ENGINEERING
Conference Paper CO-AUTHOR
2018
14 Investigation Of Parasitic Capacitance In 14nm Twin Silicon Nanowire Field Effect Transistor
2018 2ND ADVANCED RESEARCH IN ENGINEERING AND INFORMATION TECHNOLOGY (AVAREIT)
Proceedings CO-AUTHOR
2018
15 Development Of Test Pattern Generation
PROCEEDINGS OF 2017 ELECTRICAL ENGINEERING SYMPOSIUM (EES2017) - VOL 3
Proceedings UTM FIRST AUTHOR
2017
16 Secure File Transfer Using Openssl
RECENT ADVANCES IN HARDWARE SOFTWARE CO-DESIGN & PATTERN RECOGNITION
Book Chapter CO-AUTHOR
2017
17 Simulation And Electrical Characterization Of 3-D N-Channel And P-Channel Twin Silicon Nanowire Mosfet
MICRO-NANO SYSTEMS ENGINEERING VOL.3
Book Chapter CO-AUTHOR
2017
18 Test Register Insertion At Rtl Based On Reduced Bist
JURNAL TEKNOLOGI
Publication In Web Of Science CORRESPONDING AUTHOR
2017
19
DEMAND-DRIVEN INNOVATION PROJECT KPM - WISE COFFEE BEANS ROASTING AUTOMATION
Clasified/Technical Report CORRESPONDING AUTHOR
2016
20
LAB SHEETS CAPSTONE PROJECT DESIGN
Clasified/Technical Report CORRESPONDING AUTHOR
2016
21 Design For Testability (Dft) At Register Transfer Level (Rtl) For Greatest Common Divisor (Gcd) And Finite Impulse Respond (Fir) Circuit
2016 ELECTRICAL ENGINEERING SYMPOSIUM
Proceedings UTM FIRST AUTHOR
2016
22
DEMAND-DRIVEN INNOVATION PROJECT KPM - AUTOMATIC COCONUT DRYER BY GAS
Clasified/Technical Report CO-AUTHOR
2016
23
DESIGN FOR TESTABILITY METHOD AT REGISTER TRANSFER LEVEL
Clasified/Technical Report INDIVIDUAL AUTHOR
2016
24
FRGS - SIGNAL INTERPRETED PETRI NET MODELLING FOR HIGH PERFORMANCE PROGRAMMABLE LOGIC CONTROLLER
Clasified/Technical Report CO-AUTHOR
2016
25
END REPORT PROJECT GRANT GUP - BUILT-IN SELF-TEST FOR FUNCTIONAL REGISTER TRANSFER LEVEL
Clasified/Technical Report INDIVIDUAL AUTHOR
2016
26
DEMAND-DRIVEN INNOVATION PROJECT KPM - BATTERY ACID FILLING SYSTEM
Clasified/Technical Report CO-AUTHOR
2016
27 Built-In Self-Test For Functional Register-Transfer Level Using Assignment Decision Diagram
PROCEEDINGS OF THE IEEE TWELFTH INTERNATIONAL WORKSHOP ON RTL AND HIGH LEVEL TESTING (WRTLT'11)
Proceedings CORRESPONDING AUTHOR
2011
28 A New Class Of Easily Testable Assignment Decision Diagrams
MALAYSIAN JOURNAL OF COMPUTER SCIENCE
Publication In Web Of Science CORRESPONDING AUTHOR
2010
29 Design For Testability Ii: From High Level Perspective
ADVANCES IN MOCROELECTRONICS
Book Chapter CORRESPONDING AUTHOR
2008
30 A New Class Of Easily Testable Assignment Decision Diagrams
9th International Workshop on RTL and High Level Testing
Conference Paper INDIVIDUAL AUTHOR
2008

# Supervision List
1 ANAM RAJPER
HARDWARE-ACCELERATED DETECTION AND MITIGATION OF DISTRIBUTED DENIAL OF SERVICE ATTACKS IN SOFTWARE-DEFINED NETWORKS
CO-SUPERVISOR PHD ON GOING
2 MOHAMMED SULTAN AHMED MOHAMMED
RUN-TIME THERMAL MANAGEMENT FOR DARK SILICON MANY-CORE SYSTEM-ON-CHIP
CO-SUPERVISOR PHD ON GOING
3 ARBAB ALAMGIR
DIVERSE TEST PATTERN GENERATION FOR HIGH FAULT COVERAGE IN BLACKBOX TESTING ENVIRONMENT.
CO-SUPERVISOR PHD ON GOING
4 LIM YONG SHAN

SUPERVISOR MASTER GRADUATED
5 LIM CHIN BENG

SUPERVISOR MASTER GRADUATED
6 NUR ATIQAH BINTI ABDUL LATIB
BLUETOOTH LOW ENERGY LINK LAYER CONTROLLER IMPLEMENTATION USING DATAFLOW PROGRAMMING
CO-SUPERVISOR MASTER GRADUATED
7 TIMOTHY TIAN ZHANG WAI

SUPERVISOR MASTER GRADUATED
8 NOORAISYAH NABILAH BINTI SAMSUDIN
ECG QRS CLASSIFIER ALGORITHM FOR HARDWARE IMPLEMENTATION ON FPGA
CO-SUPERVISOR MASTER

Grant

UNIVERSITY FUND
2
TOTAL

Publications

INDEXED PUBLICATION
5
NON-INDEXED PUBLICATION
1
OTHERS PUBLICATION
24
TOTAL

Supervision

DEGREE
0
MASTER
5
PHD
3
TOTAL